Advanced level 2024 centre regional mock computer science 1
Advanced level 2024 centre regional mock computer science 1
Consider the following diagram showing some hardware
component connections on a computer system:
The Hardware part within the CPU indicated by (A) in
the above diagram has a set of registers that has the
memory translation maps of the currently running
process. When given an input virtual address of the
current process it outputs the relevant physical address
(if any).
The (A) in the above diagram denotes the
A. Arithmetic and logic unit (ALU)
B. Control unit
C. L1 cache memory
D. Memory management unit
2. Which of the following is usually regarded as a
bottleneck to von-Neumann computer Architecture?
A. ALU
B. Instruction set
C. Processor/memory interface
D. Control unit
3. The sequence of events that happen during the fetch
phase of the machine instruction cycle is:
A. PC→Memory→MAR→MDR→IR
B. PC→IR→MDR→MAR→Memory
C. PC→MAR→Memory→MDR→IR
D. PC→MDR→ 𝑀𝐴𝑅 →Memory→IR
4. Which of the following correctly list the given computer
components in the descending order of access speed?
A. Cache memory > main memory > magnetic disk >
register
B. Register > cache memory > main memory >
magnetic disk
C. Magnetic disk > main memory > cache memory >
register
D. Magnetic disk > main memory > register > cache
memory
Use the following to answer question 5, and 6
A two-word instruction LOAD is stored at location 300
with its address field in the next location. The address
field has value 600 and value stored at 600 is 500 and at
500 is 650. The words stored at 900, 901 and 902 are
400, 401 and 402, respectively. A processor register R
contains the number 800 and index register has value
100.
Memory layout is shown adjacent
5. What is the effective address of the operand and operand
value if addressing mode of the instruction is the
Memory Indirect addressing mode?
A. 600, 500
B. 500, 650
C. 301, 600
D. 600, 401
6. What is the effective address of the operand and operand
value if addressing mode of the instruction is the
Immediate addressing mode?
A. 301, 600
B. 600, 500
C. 700, 900,
D. 901, 401
7. To design a combinational logic circuit to add two 4-bit
numbers, ____ half adder and _______ full adder
circuits are needed.
A. (2, 2)
B. (1, 3)
C. (3, 1)
D. (4, 1)
8. Which of the following is the most simplified expression
equivalent to 𝐴𝐵̅𝐶̅ + 𝐵𝐶̅ + 𝐴̅𝐵̅𝐶 + 𝐵𝐶?
A. 𝐴𝐵̅𝐶̅ + 𝐴̅𝐵̅𝐶 + 𝐵
B. 𝐵̅(𝐴𝐶̅ + 𝐴̅𝐶) + 𝐵
C. 𝐴𝐶̅ + 𝐴̅𝐶 + 𝐵
D. 𝐴̅𝐶̅ + 𝐵
Consider the following logic circuit below to answer 9
and 10.
9. Which of the following statement(s) is/are correct about
the above circuit?
I – It implements a full adder.
II – the Logic function S can be stated as
𝑆 = 𝐴 ⊕ 𝐵 ⊕ 𝐶𝑖𝑛
III – the logic function of 𝐶𝑜𝑢𝑡 can be stated as 𝐶𝑜𝑢𝑡 =
𝐴𝐵 + 𝐵𝐶𝑖𝑛 + 𝐴𝐶𝑖𝑛
A. I only
B. II only
C. II and III only
D. All I, II, and III.
10. Which of the following statement(s) is/are correct about
the part of the circuit within the area surrounded by the
dotted line?
I – It implements a half adder
II – It can be implemented using only AND and OR
gates.
III – It can be implemented using only NAND gate.
A. I only
B. II only
C. I and III only
D. All I, II, and III
